RISC-V /Debug /System Bus Access Control and Status (sbcs)

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Interpret as System Bus Access Control and Status (sbcs)

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (sbaccess8)sbaccess8 0 (sbaccess16)sbaccess16 0 (sbaccess32)sbaccess32 0 (sbaccess64)sbaccess64 0 (sbaccess128)sbaccess128 0sbasize0 (none)sberror 0 (sbreadondata)sbreadondata 0 (sbautoincrement)sbautoincrement 0 (8bit)sbaccess 0 (sbreadonaddr)sbreadonaddr 0 (sbbusy)sbbusy 0 (sbbusyerror)sbbusyerror 0 (legacy)sbversion

sberror=none, sbaccess=8bit, sbversion=legacy

Description

Fields

sbaccess8

1 when 8-bit system bus accesses are supported.

sbaccess16

1 when 16-bit system bus accesses are supported.

sbaccess32

1 when 32-bit system bus accesses are supported.

sbaccess64

1 when 64-bit system bus accesses are supported.

sbaccess128

1 when 128-bit system bus accesses are supported.

sbasize

Width of system bus addresses in bits. (0 indicates there is no bus access support.)

sberror

When the Debug Module’s system bus manager encounters an error, this field gets set. The bits in this field remain set until they are cleared by writing 1 to them. While this field is non-zero, no more system bus accesses can be initiated by the Debug Module.

An implementation may report ``Other’’ (7) for any error condition.

0 (none): There was no bus error.

1 (timeout): There was a timeout.

2 (address): A bad address was accessed.

3 (alignment): There was an alignment error.

4 (size): An access of unsupported size was requested.

7 (other): Other.

sbreadondata

When 1, every read from {dm-sbdata0} automatically triggers a system bus read at the (possibly auto-incremented) address.

sbautoincrement

When 1, sbaddress is incremented by the access size (in bytes) selected in {sbcs-sbaccess} after every system bus access.

sbaccess

Select the access size to use for system bus accesses.

0 (8bit): 8-bit

1 (16bit): 16-bit

2 (32bit): 32-bit

3 (64bit): 64-bit

4 (128bit): 128-bit

sbreadonaddr

When 1, every write to {dm-sbaddress0} automatically triggers a system bus read at the new address.

sbbusy

When 1, indicates the system bus manager is busy. (Whether the system bus itself is busy is related, but not the same thing.) This bit goes high immediately when a read or write is requested for any reason, and does not go low until the access is fully completed.

Writes to {dm-sbcs} while {sbcs-sbbusy} is high result in undefined behavior. A debugger must not write to {dm-sbcs} until it reads {sbcs-sbbusy} as 0.

sbbusyerror

Set when the debugger attempts to read data while a read is in progress, or when the debugger initiates a new access while one is already in progress (while {sbcs-sbbusy} is set). It remains set until it’s explicitly cleared by the debugger.

While this field is set, no more system bus accesses can be initiated by the Debug Module.

sbversion

0 (legacy): The System Bus interface conforms to mainline drafts of this spec older than 1 January, 2018.

1 (1.0): The System Bus interface conforms to this version of the spec.

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